1. Field of the Invention
The present invention relates to a memory module, and particularly to an improved memory module which is capable of decreasing an operational current by reducing the number of operational devices in the memory module.
2. Description of the Background Art
FIG. 1 illustrates a first known memory module which is configured as a 1 BANK 8CAS 4M.times.64 device provided with four 64M (4K Refresh.times.16) DRAMs (Dynamic Random Access Memories) M1 through M4 which receive various externally supplied control signals.
FIG. 2 illustrates a second known memory module which is configured as a 1 BANK 8CAS 4M.times.64 device provided with sixteen 16M (4K Refresh.times.4) DRAM M11 through M26 which receive various externally supplied control signals. In this regard, the above-described control signals denote a row address strobe signal /RAS, address signals A0 through A11, a write enable signal /WE, an output enable signal /OE, column address strobe signals /CAS0 through /CAS7, and data input/output signals IO0 through IO63.
The operations of the above-described first and second known memory modules will be explained with reference to the accompanying drawings.
First, as shown in FIG. 1, when the row address strobe signal /RAS is low level (active), four DRAMs M1 through M4 each receive address signals A0 through A11 and internally select an X-address signal.
The DRAMs M1 through M4 receive address signals A0 through A9 in accordance with column address strobe signals /CAOS through /CAS7 and internally select a Y-address signals. At this time, if the write enable signal /WE is low level (active), the DRAMs M1 through M4 perform a write operation in accordance with the data input/output signals IO0 through IO63, and if the output enable signal /OE is low level (active), the DRAMs M1 through M4 perform a read operation.
In addition, when the column strobe signals /CAS0 through /CAS7 first become low level (active) and are applied earlier than the row address strobe signals /RAS, the DRAMs M1 through M4 perform a refresh operation.
The second known memory module is operated similarly to the first known memory module. The 16M DRAMS M11 through M26 are concurrently operated in accordance with the row address strobe signal /RAS and column address strobe signals /CAS0 through /CAS7 which are externally applied. Accordingly, further detailed description thereof will be omitted.
Since the four 64M DRAMs which are employed as the first known memory module are more expensive than sixteen 16M DRAMs which are employed as the second memory module, in order to decrease the fabrication cost, sixteen 16M DRAMS are generally used for fabricating a 32M byte module.
When adapting the memory organization of the first known module for the second known module, only four 64 DRAMs are used in the first known art. However, in the second known module, sixteen 16M DRAMs are used and operated, so that the operational current is increased by about four times.